Recent improvements in performance capabilities of data processors have included increasing the clock speed or adding additional execution units.
Alternatively, field programmable gate arrays (FPGAs) have been considered for either augmenting or replacing microprocessors in order to expand the limitations posed by the arithmetic logic units. Wholesale replacement of microprocessors with FPGAs generally requires the entire recoding of operating systems. On the other hand, redesigning microprocessors to include FPGA-like architecture presents its own set of design errors.
Therefore, a need has been perceived for a quick and safe way to enhance the arithmetic performance of microprocessors and to implement algorithms within reconfigurable hardware.